VIAVI PCIe6 protocol analysis solutions are capable of supporting 64GT/s data link speed operations with support for CXL and NVMe—as well as new PCIe6 specification features like PCIe FLIT Mode, FEC and TS0 Ordered Set. This VIAVI protocol testing platform enables bandwidth-intensive data center/hyperscale, AI/ML and high- performance computing (HPC) and networking applications.
Designed for tool versatility, the comprehensive VIAVI Xgig PCIe 6.0 platform features Analyzer and Exerciser functionality on the same chassis, augmented with application-specific interposers. This architecture optimizes signal integrity at PCIe6, while limiting the amount of individual hardware engineers and lab managers need to purchase, coordinate and maintain. It also accommodates PCIe 6.0 64GT/s trace capture and analysis on existing Xgig PCIe 5.0 equipment. The result? Optimized tool utilization, extended lifecycle for previous equipment investments, and reduced overall ownership costs.
The transition from PCIe 5.0 to PCIe 6.0 brought significant changes at the protocol level—and with it, the need for strong analysis tools to fully understand protocol behavior. Designed for PCIe “power users”, the robust Xgig PCIe6 platform enables capture and decoding of the most complex PCIe, CXL and NVMe testing scenarios. The Xgig Analyzer provides the foundation for deep protocol insights from Xgig Expert software—combining to provide users with incredible utility and flexibility in analyzing and debugging protocol issues.
Xgig 16-Lane Analyzer/Exerciser for PCI Express 6.0
The VIAVI Solutions Xgig® 16-Lane Exerciser for PCI Express® 6.0 brings the next generation of high-speed 64GT/s test capability to the Xgig PCIe product portfolio. The Exerciser is a valuable tool for debugging difficult protocol communication problems because it provides full, bit-level, repeatable control for generated PCIe 6.0, CXL and NVMe data traffic. The Analyzer allows detailed view of traffic between a host and endpoint device, supporting PCIe FLIT Mode, Non-Flit Mode, CXL, and NVMe. Exerciser and Analyzer functionality is provided via a multi-function chassis and application-specific Analyzer or Exerciser Interposers.
Benefits
- Fully integrated Analyzer/Exerciser enables a variety of test conditions
- Enables capture and decoding of the most complex PCIe, CXL and NVMe test cases
- Maximum flexibility in analyzing and debugging protocol issues
- Powerful graphical control interface provides quick status information and rapid test case set-up
- Optimizes signal integrity at PCIe6
- Quicker time to market and earlier revenue
- Lower engineering costs
Applications
- Analyzer allows detailed view of traffic between a host and endpoint device, supporting PCIe FLIT Mode, Non-Flit Mode, CXL and NVMe specifications
- Allows capture and analysis of traffic flows between the Exerciser and its link partner
- Exerciser emulates the operation of a Root Complex (RC) or an Endpoint (EP) device
- Enables bandwidth intensive applications like High-Performance Computing and Artificial Intelligence needed by hyperscalers and other providers
Highlights
- Operates up to 64GT/s PAM4, PCIe 6.0 data rates
- Downward compatible with PCIe 1.0, 2.0, 3.0, 4.0 and 5.0, and data rates of 2.5, 5.0, 8.0, 16 and 32GT/s NRZ
- Supports link widths of 1, 2, 4, 8 and 16-lanes
- 64GB total memory (32GB upstream capture and 32GB downstream capture)
- User can set Exerciser link rates and widths and control transitions to other rates
- Fully integrated Analyzer/Exerciser enables a variety of test conditions
- Support for new PCIe FLIT Mode, FEC and TS0 Ordered Set
- LTSSM state tracker with history log
- User can define and save custom test configurations
- Scripting API allows creation of complex, user-defined test cases
- Supported by VIAVI Xgig tool suite including Trace Control, Expert and Serialytics
Xgig 4-Lane Exerciser for PCI Express 6.0
The VIAVI Solutions Xgig® 4-Lane Exerciser for PCI Express® 6.0 is a valuable tool for debugging difficult protocol communication problems. This 6P4 Exerciser can be configured to emulate the operation of a Root Complex (RC) or an Endpoint (EP) device, effectively acting as a highly-configurable link partner for testing Hosts and Endpoint devices. The 6P4 has built-in analysis capabilities and is enabled automatically to capture full duplex data between the Exerciser and its link partner. This is a fully integrated solution with Exerciser functionality provided in a single CEM card form factor.
Benefits
- Enables capture and decoding of the most complex PCIe, CXL and NVMe test cases
- Maximum flexibility in analyzing and debugging protocol issues
- Powerful graphical control interface provides quick status information and rapid test case set-up
- Optimizes signal integrity at PCIe6
- Quicker time to market and earlier revenue
- Lower engineering costs
Applications
- Allows capture and analysis of traffic flows between the Exerciser and its link partner
- Emulates the operation of a Root Complex (RC) or an Endpoint (EP) device
- Supports CXL and NVMe specifications
- Enables bandwidth intensive applications like High-Performance Computing and Artificial Intelligence needed by hyperscalers and other providers
Highlights
- Operates up to 64GT/s PAM4, PCIe 6.0 data rates
- Downward compatible with PCIe 1.0, 2.0, 3.0, 4.0 and 5.0, and data rates of 2.5, 5.0, 8.0, 16 and 32GT/s NRZ
- Supports link widths of 1, 2, and 4-lanes
- 32GB total memory (16GB upstream capture and 16GB downstream capture)
- User can set link rates and widths and control transitions to other rates
- Fully integrated Analyzer function enables a variety of test conditions
- Support for new PCIe FLIT Mode, FEC and TS0 Ordered Set
- LTSSM state tracker with history log
- User-configurable custom test configurations for positive and negative test cases
- Scripting API allows creation of complex, user-defined test cases
- Supported by VIAVI Xgig tool suite including Trace Control, Expert and Serialytics